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[rtl] refactor mask unit. #788

Merged
merged 6 commits into from
Nov 17, 2024
Merged

[rtl] refactor mask unit. #788

merged 6 commits into from
Nov 17, 2024

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qinjun-li
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val stageClear: Bool = IO(Output(Bool()))

val stageClearVec: Seq[Bool] = in.zipWithIndex.map { case (req, index) =>
val reqQueue = Queue(req, 4)
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Use DWBB queue

val readData = readResult(index)
val res = out(index)

val WaitReadQueue: Queue[BitLevelWriteRequest] = Module(new Queue(chiselTypeOf(req.bits), readVRFLatency))
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Use DWBB queue

@qinjun-li qinjun-li force-pushed the mask-unit branch 5 times, most recently from f5dff9f to d038fc2 Compare November 3, 2024 09:20
qinjun-li and others added 4 commits November 17, 2024 21:30
Report CI result at final step might fail when RTL changes causing
online driver to fail. And developers might find it hard to get a list
of fail tests list to get fixed. This commit move the report step at
running stage.

Signed-off-by: Avimitin <[email protected]>
@sequencer sequencer merged commit ec149cc into master Nov 17, 2024
@sequencer sequencer deleted the mask-unit branch November 17, 2024 14:35
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3 participants