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Added Verilog-AMS Syntax Highlighter #858

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Added Verilog-AMS Syntax Highlighter

Added Verilog-AMS Syntax Highlighter #858

Re-run triggered January 23, 2025 02:08
@mshr-hmshr-h
#515
Hypothawits:vams_highlighting
Status Success
Total duration 1m 22s
Artifacts 1

ci.yml

on: pull_request
Matrix: Upload vsix package
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31 warnings
Upload vsix package (macos-latest): src/commands/ModuleInstantiation.ts#L51
Expected '!==' and instead saw '!='
Upload vsix package (macos-latest): src/ctags.ts#L203
Expected '===' and instead saw '=='
Upload vsix package (macos-latest): src/hover.ts#L117
Unexpected constant condition
Upload vsix package (macos-latest): src/linter/ModelsimLinter.ts#L7
'process' is not defined
Upload vsix package (macos-latest): src/linter/ModelsimLinter.ts#L50
Expected '===' and instead saw '=='
Upload vsix package (macos-latest): src/linter/ModelsimLinter.ts#L53
Expected '===' and instead saw '=='
Upload vsix package (macos-latest): src/linter/ModelsimLinter.ts#L79
Expected '!==' and instead saw '!='
Upload vsix package (macos-latest): src/linter/XvlogLinter.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (macos-latest): src/providers/FormatPrivider.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (macos-latest): src/providers/FormatPrivider.ts#L26
'BufferEncoding' is not defined
Upload vsix package (ubuntu-latest)
ubuntu-latest pipelines will use ubuntu-24.04 soon. For more details, see https://github.com/actions/runner-images/issues/10636
Upload vsix package (ubuntu-latest): src/commands/ModuleInstantiation.ts#L51
Expected '!==' and instead saw '!='
Upload vsix package (ubuntu-latest): src/ctags.ts#L203
Expected '===' and instead saw '=='
Upload vsix package (ubuntu-latest): src/hover.ts#L117
Unexpected constant condition
Upload vsix package (ubuntu-latest): src/linter/ModelsimLinter.ts#L7
'process' is not defined
Upload vsix package (ubuntu-latest): src/linter/ModelsimLinter.ts#L50
Expected '===' and instead saw '=='
Upload vsix package (ubuntu-latest): src/linter/ModelsimLinter.ts#L53
Expected '===' and instead saw '=='
Upload vsix package (ubuntu-latest): src/linter/ModelsimLinter.ts#L79
Expected '!==' and instead saw '!='
Upload vsix package (ubuntu-latest): src/linter/XvlogLinter.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (ubuntu-latest): src/providers/FormatPrivider.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (ubuntu-latest): src/providers/FormatPrivider.ts#L26
'BufferEncoding' is not defined
Upload vsix package (windows-latest): src/commands/ModuleInstantiation.ts#L51
Expected '!==' and instead saw '!='
Upload vsix package (windows-latest): src/ctags.ts#L203
Expected '===' and instead saw '=='
Upload vsix package (windows-latest): src/hover.ts#L117
Unexpected constant condition
Upload vsix package (windows-latest): src/linter/ModelsimLinter.ts#L7
'process' is not defined
Upload vsix package (windows-latest): src/linter/ModelsimLinter.ts#L50
Expected '===' and instead saw '=='
Upload vsix package (windows-latest): src/linter/ModelsimLinter.ts#L53
Expected '===' and instead saw '=='
Upload vsix package (windows-latest): src/linter/ModelsimLinter.ts#L79
Expected '!==' and instead saw '!='
Upload vsix package (windows-latest): src/linter/XvlogLinter.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (windows-latest): src/providers/FormatPrivider.ts#L3
Import name `child_process` must match one of the following formats: camelCase, PascalCase
Upload vsix package (windows-latest): src/providers/FormatPrivider.ts#L26
'BufferEncoding' is not defined

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