Added Verilog-AMS Syntax Highlighter · mshr-h/vscode-verilog-hdl-support@1d05102

npm test: src/commands/ModuleInstantiation.ts#L51

Expected '!==' and instead saw '!='

npm test: src/ctags.ts#L203

Expected '===' and instead saw '=='

npm test: src/hover.ts#L117

Unexpected constant condition

npm test: src/linter/ModelsimLinter.ts#L7

'process' is not defined

npm test: src/linter/ModelsimLinter.ts#L50

Expected '===' and instead saw '=='

npm test: src/linter/ModelsimLinter.ts#L53

Expected '===' and instead saw '=='

npm test: src/linter/ModelsimLinter.ts#L79

Expected '!==' and instead saw '!='

npm test: src/linter/XvlogLinter.ts#L3

Import name `child_process` must match one of the following formats: camelCase, PascalCase

npm test: src/providers/FormatPrivider.ts#L3

Import name `child_process` must match one of the following formats: camelCase, PascalCase

npm test: src/providers/FormatPrivider.ts#L26

'BufferEncoding' is not defined

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